Co-Optimized Semiconductor Design Platform for Advanced Node Artificial Intelligence

Samsung Foundry and Cadence Design Systems have expanded their technical collaboration to deliver a co-optimized electronic design automation and intellectual property platform for advanced semiconductor manufacturing. The joint framework targets high-performance computing, digital infrastructure, and physical artificial intelligence hardware deployed in edge robotics, autonomous systems, and hyperscale data centers.

Technical Architecture and Operational Integration
Sub-2nm manufacturing presents significant challenges regarding interconnect resistance, thermal dissipation, and signal integrity across multi-die packages. To manage these constraints, the partners combined Samsung Foundry's 2nm Gate-All-Around (GAA) process with Cadence's certified implementation, verification, and signoff workflows.

The fabrication node integrates nanosheet architectures with hyper cell configurations and low-resistance redistribution layers (RDL) to reduce power dissipation and optimize cell height. Cadence links its software toolchains directly to these silicon parameters, integrating GPU-accelerated computing libraries via Nvidia CUDA-X to run compute-intensive physical verification on dedicated supercomputing clusters.

Interface Standards and Packaging
The joint platform provides verified interface and memory IP designed for high-bandwidth multi-die architectures, including:

For vertical multi-die integration, Cadence workflows support Samsung's 3D Cube-H packaging methodology. This technology uses Hybrid Copper Bonding (HCB) to establish direct copper-to-copper contacts between stacked dies, bypassing microbumps to minimize parasitic capacitance and reduce thermal-induced mechanical stress.

Deployment and Edge Applications
The integrated toolchain is deployed across design teams developing custom accelerated computing chips and edge perception silicon. Nvidia uses Cadence tools targeting Samsung's second-generation 2nm process to construct multi-die compute topologies. Concurrently, Ambarella deploys the platform to build edge systems that process real-time multimodal sensor data, vision-language models, and large language models for autonomous machines.

System Validation and Efficiency Impacts
By aligning physical design rules directly with signoff simulation models, the platform accelerates power, performance, and area (PPA) convergence. Pre-validated intellectual property blocks eliminate manual routing iterations for high-speed buses, lowering the risk of post-tapeout silicon failures. The tight integration between physical bonding standards and automated layout tools enables determinism in multi-die thermal distribution, reducing turnaround times for high-density edge and data center accelerators.

Edited by Natania Lyngdoh, Induportals editor, assisted by AI.

www.semiconductor.samsung.com