Pickering Exhibits Semiconductor Test Switching at Microelectronics UK

Pickering Interfaces will exhibit its industry-standard modular signal switching solutions for semiconductor testing and verification at Microelectronics UK, held September 29–30, 2026, at Excel London. The showcase will focus on specialized switching architectures that deliver precise signal routing and low leakage, designed for rigorous applications such as wafer acceptance testing, photonics testing, and high pin-count package validation.

Among the hardware highlights on stand E42, Pickering will display its LXI reed relay plug-in matrix (65-221), which features a dual 128x4 configuration originally developed for parametric testing. The exhibit will also feature a 12-slot BRIC PXI matrix (40-558) for ultra-high-density applications, an LXI switched guard plug-in matrix offering isolation resistance up to 10¹²Omega for precise low-level measurements, and a fully compliant 7-slot LXI/USB modular chassis. Additionally, Pickering will demonstrate its newly launched Test System Architect, a free online graphical design tool that enables engineers to configure and visualize complete signal paths and automated cable designs before physical deployment.

Additional Context
This section provides technological and market background not explicitly detailed in the original release.

In semiconductor manufacturing, parametric testing validates the electrical properties of individual components on a wafer using Source/Measurement Units (SMUs). Because these measurements often involve extremely low currents or voltages, the switching matrix connecting the SMUs to the Device Under Test (DUT) must minimize signal degradation and leakage. Pickering's 65-221 modular matrix achieves this by utilizing instrumentation-grade reed relays, allowing up to 12 SMUs to connect simultaneously for large-scale, 4-wire parallel testing. Furthermore, designing the complex signal routing for such automated test equipment (ATE) traditionally required manual spreadsheets, which often led to costly wiring errors and delays. The cloud-based Test System Architect platform addresses this bottleneck by replacing manual pin-mapping with an intuitive graphical interface, which can reduce signal-path design time by up to 25% while automatically generating wiring schematics, datasheets, and bills of materials.

Edited by Lekshman Ramdas, Induportals editor – adapted by AI.

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