Murata Heads to Hot Chips 2026

Murata will showcase electronic components and power technologies designed for artificial intelligence (AI) infrastructure at Hot Chips 2026. The conference will take place from August 23 to 25, 2026, in Palo Alto, California.

Electronic Component and Power Delivery Portfolio
Murata's exhibit focuses on hardware solutions that support AI systems at physical implementation boundaries. The showcase includes technologies for advanced semiconductor packaging, high-density power delivery architectures, high-speed connectivity, and next-generation computing platforms.

These electronic components and power technologies are engineered to address power, thermal, and spatial constraints encountered in AI hardware designs. The hardware applications target multiple sectors, including mobility, industrial automation, medical technology (MedTech), agricultural technology (AgriTech), robotics, and data centers.

Event Demonstrations and Applications
At its conference booth, Murata will demonstrate how compact electronic components and clean power solutions support agentic AI deployments across high-density computing platforms. The demonstrations aim to show how hardware efficiency and reliability enable AI processing to interact directly with physical systems.

Additional Context
This section details technical specifications not included in the original news release.

Advanced AI computing architectures, such as multi-die accelerators and High Bandwidth Memory (HBM) stacks, demand high power densities and transient response capabilities from local Power Delivery Networks (PDNs). Voltage regulator modules (VRMs) powering high-performance GPUs and AI System-on-Chips (SoCs) face extreme current slew rates where supply current demands fluctuate rapidly within nanosecond intervals. To stabilize power rails and prevent voltage droop, high-density power delivery architectures rely on low Equivalent Series Inductance (ESL) and low Equivalent Series Resistance (ESR) multi-layer ceramic capacitors (MLCCs) placed in close proximity to the processor die or directly within the IC substrate.

In 2.5D and 3D heterogeneous semiconductor packaging, silicon interposers and organic substrates integrate silicon capacitors (Si-caps) and ultra-thin ceramic passive components. Embedded passive substrates minimize parasitic loop inductance between the power management integrated circuits (PMICs) and core logic dies.

Furthermore, high-speed signal integrity across 112 Gbps and 224 Gbps PAM4 SerDes interconnects requires precise impedance matching and noise suppression. Signal line filtering utilizes compact common-mode choke coils, low-loss RF inductors, and specialized EMI suppression filters to maintain signal clarity and reduce crosstalk in high-density data center backplanes and optical transceivers.

Edited by Romila DSilva, Induportals Editor, with AI assistance.