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Miniature Low-ESL MLCC Technology for High-Frequency Power Decoupling
Murata begins mass production of 0201-inch three-terminal MLCCs in the LLD series to minimize parasitic inductance in space-constrained mobile electronics.
www.murata.com
Advanced system-on-chip architectures and multi-core application processors operating at gigahertz frequencies generate sharp transient current steps that induce steep voltage dips across power distribution networks. When high di/dt switching transitions encounter parasitic equivalent series inductance (ESL) within conventional decoupling loops, the resulting voltage ripple threatens logic threshold stability and degrades processor clocking integrity. To eliminate these high-frequency supply fluctuations within densely populated board layouts, Murata Manufacturing Co., Ltd. initiated mass production of its LLD series, delivering three-terminal low-ESL multilayer ceramic capacitors (MLCCs) engineered in the ultra-miniature 0201-inch (0603 metric) surface-mount package.
High di/dt Transients and Power Distribution Network Impedance
Modern ultra-thin smartphones, continuous health monitors, and wearable hardware demand tighter integration of high-density processor silicon alongside shrinking printed circuit board (PCB) surface areas. As processor supply rails transition to lower operating voltages (often sub-1.0 V) with higher currents, allowable voltage margins contract severely. Standard decoupling implementations rely on parallel arrays of standard two-terminal capacitors to depress impedance across broad frequency bands.
However, standard two-terminal MLCCs carry internal current flow along a single longitudinal direction, generating appreciable parasitic loop inductance that limits attenuation above tens of megahertz. While three-terminal low-ESL components have historically provided superior high-frequency attenuation, their complex interdigitated internal electrode layers and multi-contact side terminations made miniaturization below the 0402-inch form factor technically difficult due to physical alignment limits and dielectric layer thinning constraints.
Electrode Geometric Optimization in 0201 Form Factor
Murata resolved these packaging limitations through precision thin-film dielectric layering and re-engineered internal electrode patterns. Measuring 0.6 mm in length by 0.3 mm in width, the 0201-inch LLD series reduces PCB footprint area by approximately 64 percent compared to previous-generation 0402-inch (1.0 mm × 0.5 mm) devices.
The three-terminal architecture alters the internal current loop by dividing displacement current into four shorter parallel return paths:
- Ground terminations positioned on the lateral edges shorten current transit distance through the capacitor structure.
- Opposing high-frequency currents establish mutual electromagnetic cancellation, suppressing self-inductance.
- The resulting low ESL characteristic pushes the capacitor's self-resonant frequency (SRF) into higher frequency bands, suppressing impedance in the 100 MHz to 1 GHz range.
- Designers can place the passive component immediately adjacent to application processor power balls, eliminating trace inductance between the component and silicon die.
Technical Specifications of the LLD Series
Mass production comprises two distinct commercial configurations optimized for consumer mobile power rails:
- Part number LLD033R60G105ME01 provides 1.0 μF capacitance with a rated voltage of 4.0 Vdc, operating within a temperature envelope of -55 to +85 degrees Celsius under the X5R dielectric specification.
- Part number LLD033D80E105ME01 provides 1.0 μF capacitance with a rated voltage of 2.5 Vdc, rated for an extended thermal range of -55 to +105 degrees Celsius under the X6T dielectric specification.
Both variants deliver low-impedance decoupling in space-constrained mobile platforms, allowing engineers to replace multiple parallel two-terminal passives with a single multi-terminal device.
Additional Context:
This section details technical specifications and competitive benchmarking not included in the original product announcement.
Passive component benchmarking within power distribution network (PDN) design evaluates equivalent series inductance (ESL) and the resulting impedance profile under high-speed load steps. Conventional 0201-size two-terminal MLCCs exhibit typical ESL values ranging from 200 pH to 400 pH, primarily determined by distance between opposing end terminations and internal current path length. In contrast, three-terminal feedthrough/shunt MLCC geometries achieve ESL ratings typically between 30 pH and 80 pH, delivering a four- to five-fold reduction in inductive parasitics.
In the miniaturized decoupling capacitor sector, Murata competes against passive component manufacturers such as TDK Corporation and Samsung Electro-Mechanics (SEMCO). While reverse-geometry standard two-terminal capacitors (such as 0306-inch or 0204-inch LW-reversed components) achieve moderate ESL reduction by placing terminations along the long edge of the component (typically lowering inductance to approximately 100 pH to 150 pH), they retain standard dipole configurations. TDK and Samsung produce three-terminal and low-ESL components primarily in 0402-inch (1005 metric) and 0503-inch form factors for automotive and core processor rails. By scaling the three-terminal four-path architecture down to the 0201-inch (0603 metric) envelope at 1.0 μF capacitance, the LLD series establishes a new density benchmark for decoupling sub-1-volt high-frequency rails directly beneath or adjacent to fine-pitch wafer-level chip-scale packages (WLCSP).
Edited by Natania Lyngdoh, Induportals editor, with AI assistance.
www.murata.com
Additional Context:
This section details technical specifications and competitive benchmarking not included in the original product announcement.
Passive component benchmarking within power distribution network (PDN) design evaluates equivalent series inductance (ESL) and the resulting impedance profile under high-speed load steps. Conventional 0201-size two-terminal MLCCs exhibit typical ESL values ranging from 200 pH to 400 pH, primarily determined by distance between opposing end terminations and internal current path length. In contrast, three-terminal feedthrough/shunt MLCC geometries achieve ESL ratings typically between 30 pH and 80 pH, delivering a four- to five-fold reduction in inductive parasitics.
In the miniaturized decoupling capacitor sector, Murata competes against passive component manufacturers such as TDK Corporation and Samsung Electro-Mechanics (SEMCO). While reverse-geometry standard two-terminal capacitors (such as 0306-inch or 0204-inch LW-reversed components) achieve moderate ESL reduction by placing terminations along the long edge of the component (typically lowering inductance to approximately 100 pH to 150 pH), they retain standard dipole configurations. TDK and Samsung produce three-terminal and low-ESL components primarily in 0402-inch (1005 metric) and 0503-inch form factors for automotive and core processor rails. By scaling the three-terminal four-path architecture down to the 0201-inch (0603 metric) envelope at 1.0 μF capacitance, the LLD series establishes a new density benchmark for decoupling sub-1-volt high-frequency rails directly beneath or adjacent to fine-pitch wafer-level chip-scale packages (WLCSP).
Edited by Natania Lyngdoh, Induportals editor, with AI assistance.
www.murata.com
