Dual-Side Cooled GaN for AI Data Centers

High-density power conversion in artificial intelligence infrastructure faces severe physical bottlenecks as server rack demands shift from 120 kW toward megawatt-scale envelopes. Supplying multi-megawatt computing power within limited data center footprints requires primary power stages to handle higher currents without exceeding thermal thresholds or occupying excessive printed circuit board area. Conventional semiconductor packaging options, including single-side or top-side-cooled packages, often restrict the heat flow to single conduction paths, compelling hardware engineers to oversize heat sinks, derate system power throughput, or restrict overall packaging density in high-voltage DC distribution networks.

Thermal Management in Megawatt Server Architectures
To address these physical limits, the TP65H020G4PLSGBD integrates dual-side cooling within an 8 x 8 mm PQFN form factor. By enabling simultaneous heat dissipation through both the top surface and the bottom lead frame soldered to the circuit board, the package lowers top-side thermal impedance by 10% compared to standard top-side-cooled packaging. The package footprint occupies 57% less surface area than legacy 10 x 15 mm Transistor Outline Leaded Top-Side (TOLT) packages.

This package layout targets the 800V intermediate bus converter (IBC) stages that step down incoming high-voltage direct current to 48V, 12V, or 6V delivery domains. It also targets the critical energy buffer stages within sidecar power racks, including battery backup units (BBU) and capacitor backup banks (CBU). By dissipating heat through two parallel paths, the package allows power engineers to increase current density per module without escalating board-level cooling hardware requirements.

Operating Mechanism and Gate-Drive Simplicity
Manufactured on Renesas Gen IV Plus GaN technology, the depletion-mode (D-Mode) transistor provides an on-state resistance of 20 mΩ and supports continuous operating levels up to 700V. The underlying wide-bandgap structure reduces gate charge and output capacitance, lowering parasitic switching losses at elevated frequencies into the megahertz range. High-frequency operation directly minimizes the physical volume and mass of associated magnetic inductors and passive components, mitigating bill-of-materials costs in power conversion modules.

The device includes an integrated freewheeling diode function that exhibits minimal reverse recovery charge, preventing high reverse-conduction energy losses during hard-switching commutations. Unlike enhancement-mode (E-Mode) alternatives that often require specialized drivers and negative gate-bias voltages to guarantee off-state stability, this configuration features a high threshold voltage compatible with standard silicon gate drivers. This design permits system designers to transition to gallium nitride power stages using conventional driver topologies without introducing negative gate-bias rails or dedicated drive circuitry.

Hardware Integration and Efficiency Benchmarks
Renesas substantiated the component layout in an 800V-to-48V unregulated LLC DC transformer (DCX) reference platform rated at 6 kW. Governed by a Renesas RA6T3 microcontroller, the reference converter operates at a volumetric power density of 2.6 kW/in³. During per-module laboratory evaluations, the dual-side-cooled implementation recorded a full-load electrical efficiency improvement of 0.21% compared against an identical circuit equipped with standard TOLT-packaged transistors.

The compact 8 x 8 mm footprint also shortens trace lengths, lowering stray loop inductances and improving geometric switching symmetry across parallel field-effect transistors. Alongside 48V output designs, the dual-side-cooled platform scales directly into 800V-to-12V and 800V-to-6V DC/DC converter designs supporting point-of-load architectures across original equipment manufacturers (OEMs), original design manufacturers (ODMs), and hyperscale operators.

Additional Context
This section details technical specifications and competitive benchmarking not included in the original product announcement.

The shift toward 800V DC power architectures in modern computing centers is directly propelled by the Open Compute Project (OCP) Open Rack standards, which seek to curb excessive conduction losses (I²R) inherent to high-current 48V and 12V busways at 100 kW+ per rack. In mainstream megawatt power infrastructure, standard 650V-rated silicon superjunction MOSFETs exhibit elevated output capacitance (C_OSS) and significant reverse-recovery charge (Q_rr), making megahertz-frequency switching practically unviable due to extreme switching losses.

While silicon carbide (SiC) MOSFETs dominate multi-kilovolt power transmission, 650V GaN-on-silicon transistors offer superior high-frequency switching figures of merit (R_DS(on) x Q_g and R_DS(on) x Q_oss) below 1 kV. In high-density topologies, standard surface-mount discrete packages such as D2PAK-7L, TO-Leadless (TOLL), and TOLT rely primarily on heat transfer into either the printed circuit board or a dedicated top-mounted cold plate. Dual-side thermal packaging addresses the high thermal resistance of conventional thick FR-4 substrates by dividing junction-to-ambient thermal resistance between board vias and liquid-cooled cold plates, establishing parity with advanced multi-phase power modules used in mission-critical high-density computing.

Edited by Evgeny Churilov, Induportals Media - Adapted by AI.

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