Microchip Advances Edge AI Sensor Connectivity

Microchip Technology has introduced Revision 2.0 of its PolarFire FPGA Ethernet Sensor Bridge, a compact, production-ready evaluation board engineered to integrate multi-sensor streams into 10Gb Ethernet architectures. The board targets high-performance edge AI applications across medical, industrial, and humanoid robotics platforms powered by NVIDIA Jetson and IGX edge computing hardware.

Hardware and Interface Enhancements
The Revision 2.0 board features a 60 percent form factor reduction compared to the first-generation release and operates via USB-C power delivery for rack deployment. The platform supports up to four camera inputs—doubling the camera capacity of the previous generation—and incorporates a camera connector compatible with NVIDIA Jetson edge modules.

For validation, the board integrates dedicated optical latency measurement circuitry. This hardware allows developers to measure end-to-end latency from image capture to AI inference execution using the NVIDIA Latency Display Analysis Tool.

Scalable Architecture and Expansion Options
The board includes an FPGA Mezzanine Card (FMC) expansion connector alongside a standard PMOD interface. Native protocol support includes MIPI CSI-2, I²C, UART, and GPIO. The system architecture accommodates adaptation to alternative sensor and video interface protocols—such as SLVS-EC 2.0, 12G-SDI, HDMI, and DisplayPort—without requiring modifications to the core processing hardware.

Software Integration and Power Management
The board processes multi-sensor data in real time over Ethernet using PolarFire FPGAs, which incorporate built-in hardware security and safety functions. Software support includes integration with the NVIDIA Holoscan SDK for access to optimized software libraries, machine learning models, and reference architectures.

The package includes hardware schematics, cameras, cabling, reference designs, and design collateral. RTL logic development is supported via the Libero SoC Design Suite. Power delivery and clock management are handled by integrated Microchip ICs—including the MCP16701 Power Management Integrated Circuit (PMIC)—which are validated specifically for PolarFire FPGA operation to ensure deterministic latency and power efficiency.

Additional Context
This section details technical specifications not included in the original news release.

Microchip PolarFire FPGAs operate on a non-volatile, flash-based process node technology that eliminates configuration memory single-event upsets (SEU) while maintaining low static power consumption relative to SRAM-based alternatives. In high-speed sensor ingestion, NVIDIA Holoscan Sensor Bridge technology leverages UDP/IP network encapsulation over Ethernet to transmit uncompressed sensor frames directly to GPU memory via Remote Direct Memory Access (RDMA), bypassing host CPU overhead and reducing overall system latency.

The FPGA Mezzanine Card (FMC) expansion port adheres to the VITA 57.1 specification, routing high-speed multi-gigabit transceivers and parallel I/O lines from the FPGA to customizable daughtercards. The integrated MCP16701 PMIC is designed to regulate core, I/O, and transceiver power rails within tight tolerances required for low-jitter clock distribution networks. RTL design synthesis within the Libero SoC Design Suite grants access to built-in cryptographic services, including Differential Power Analysis (DPA) countermeasures and secure boot configurations embedded directly within PolarFire silicon.

Edited by Romila DSilva, Induportals Editor, with AI assistance.