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Mythic Selects Microchip MemBrain Technology for Next Generation Power Efficiency
By integrating SST’s SuperFlash based analog compute-in-memory technology, Mythic aims to deliver ultra-low-power AI inference performance reaching 120 TOPS/watt for edge and data center applications.
www.microchip.com
The integration of neuromorphic hardware intellectual property into next-generation Analog Processing Units (APUs) aims to address the power consumption bottlenecks inherent in traditional digital architectures during artificial intelligence (AI) inference. By utilizing analog compute-in-memory (aCIM) techniques, these processors enable energy-efficient execution for edge computing, industrial automation, and automotive data ecosystems.
Evolution of Analog Processing Units
Traditional digital Graphics Processing Units (GPUs) often encounter energy bottlenecks when moving data between separate memory and logic components. To mitigate this, Mythic has selected the memBrain neuromorphic hardware IP from Silicon Storage Technology (SST), a subsidiary of Microchip Technology. This technology collapses the computation and storage functions into a single plane, allowing for single-cycle multiply-and-accumulate (MAC) operations directly within the memory array.
The transition to aCIM allows these next-generation APUs to target an inference performance of 120 TOPS/watt. This level of efficiency is approximately 100 times higher than that of conventional digital GPUs, making the technology suitable for power-constrained environments such as autonomous sensors and remote data centers.
Technical Specifications of memBrain Cells
The core of this architecture relies on SuperFlash embedded non-volatile memory (eNVM) bitcells. Unlike standard digital memory that stores a single bit per cell, the memBrain cell supports up to 8 bits of data storage (8 bpc) through multi-state write operations managed by a full state machine control.
Key technical parameters of the bitcells include:
- Power Consumption: Single-digit nanoamp (nA) read current per bitcell.
- Durability: 100,000 endurance cycles.
- Reliability: 10-year data retention at standard operating temperatures.
- Process Nodes: Currently deployed in 40 nm and 28 nm foundry processes, with a roadmap extending to 22 nm development.
Industrial Applications and Sensor Fusion
The deployment of these APUs is primarily focused on AI inference processing and AI sensor fusion. In industrial and automotive sectors, this facilitates real-time data analysis from multiple sensors without the latency or power overhead associated with cloud-based processing.
The use of an industry-proven eNVM solution like SuperFlash, which has seen over 150 billion units shipped globally, provides a stable foundation for scaling these analog units from edge devices to enterprise-level hardware. By integrating these components, developers can implement complex neural networks in compact form factors that require minimal heat dissipation and high computational throughput.
Market Positioning
While digital neural processors and digital-CIM (using SRAM) remain common in the semiconductor industry, the analog approach utilized by SST and Mythic differentiates itself through area efficiency and the elimination of external DRAM requirements. This multi-level cell technology specifically targets the sub-threshold region of operation to maximize performance-per-watt, providing a measurable alternative to traditional digital AI accelerators in high-density compute applications.
Edited by an industrial journalist, Evgeny Churilov.
www.microchip.com
The deployment of these APUs is primarily focused on AI inference processing and AI sensor fusion. In industrial and automotive sectors, this facilitates real-time data analysis from multiple sensors without the latency or power overhead associated with cloud-based processing.
The use of an industry-proven eNVM solution like SuperFlash, which has seen over 150 billion units shipped globally, provides a stable foundation for scaling these analog units from edge devices to enterprise-level hardware. By integrating these components, developers can implement complex neural networks in compact form factors that require minimal heat dissipation and high computational throughput.
Market Positioning
While digital neural processors and digital-CIM (using SRAM) remain common in the semiconductor industry, the analog approach utilized by SST and Mythic differentiates itself through area efficiency and the elimination of external DRAM requirements. This multi-level cell technology specifically targets the sub-threshold region of operation to maximize performance-per-watt, providing a measurable alternative to traditional digital AI accelerators in high-density compute applications.
Edited by an industrial journalist, Evgeny Churilov.
www.microchip.com
