ZF unveils scalable I/O interface chip architecture for next-generation ADAS and automated driving

ZF has introduced a new I/O interface chip architecture designed to redefine high-performance computing for Advanced Driver Assistance Systems (ADAS) and automated driving (AD). Developed in collaboration with SiliconAuto, the solution was demonstrated at Embedded World (Mar. 10 to 12), 2026 in Nuremberg.

At the core of the innovation is a modular, chiplet-ready architecture that represents a scalable and cost-efficient alternative to traditional monolithic System-on-Chip (SoC) solutions. The platform integrates a newly developed I/O interface chip with SiliconAuto’s XMotiv™ M3 microcontroller, which acts as a dedicated safety controller.

High-performance sensor integration and processing
The new I/O interface chip consolidates essential automotive sensor interface IP and integrates sensor pre-processing capabilities, including low-latency camera Image Signal Processing (ISP) and on-chip radar signal processing.

The chip is tightly coupled with the XMotiv™ M3 microcontroller, enabling secure system management functions such as fast boot, power sequencing, clock control and reset supervision. At the same time, the architecture remains agnostic to the OEM’s preferred performance SoC, leveraging standardized high-speed interfaces such as PCIe and Ethernet.

Scalable architecture from entry-level to premium vehicles
The solution is designed to support a wide range of vehicle platforms, from entry-level ADAS systems to premium automated driving applications. By offloading sensor data acquisition and pre-processing tasks from the central processor, the architecture allows the main SoC to focus on perception and driving functions, improving overall system efficiency.

In addition, the design reduces power consumption by minimizing data transfers to DDR memory and optimizing clock speeds. The I/O interface chip is also compatible with the latest low-power AI inference engines, ensuring future readiness.

Modular design for flexibility and upgradeability
Unlike conventional high-performance computing architectures, the ZF/SiliconAuto solution is:

This approach provides a clear pathway toward scalable automotive computing, from basic driver assistance to SAE Level 4 autonomous driving.

Towards an open chiplet-based ecosystem
Future development will focus on integrating open die-to-die interconnect standards such as UCIe, transforming the I/O interface into a fully compliant chiplet. This will enable OEMs to independently select and upgrade compute, AI and I/O components, ensuring long-term flexibility and data sovereignty.

Supporting sustainability and European innovation
The project was supported by the German Federal Ministry for Education, Research and Space under the ZuSEKI-mobil program, aimed at strengthening secure, sustainable microelectronics in Europe.

By adopting a modular chiplet-based architecture, the solution contributes to extending system lifecycles, reducing energy consumption and enabling more sustainable mobility technologies—reinforcing Europe’s position in next-generation automotive electronics.

Edited by Maria Brueva, Induportals editor - Adapted by AI.

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