Multi-Architecture Compiler Integrates RISC-V Automotive Processors

HighTec EDV-Systeme has released compiler support for Infineon's next-generation AURIX RC1 microcontroller family. The HighTec Embedded AI, Rust, and C/C++ Development Platform for RISC-V integrates device-specific compiler options optimized for pipeline execution and code size reduction, targeting safety-critical applications in software-defined vehicles (SDVs) and edge AI systems.

Consolidating Automotive Domains with RISC-V
The transition toward software-defined systems necessitates embedded computing platforms capable of high real-time performance while adhering to strict functional safety and cybersecurity standards. The AURIX RC1 architecture relies on a RISC-V multicore foundation designed to standardize microcontrollers across multiple automotive domains. The platform ranges from conventional MCUs to planned hybrid MCU/MPU devices featuring 64-bit processing, facilitating the consolidation of functions within centralized vehicle computers and zonal controllers. The hardware architecture incorporates up to twelve 32-bit processing cores, an enhanced Parallel Processing Unit (PPU) for edge AI execution, and up to 40 MB of embedded memory.

To support this silicon, the LLVM-based HighTec compiler toolchain is qualified to ISO 26262 up to ASIL D for functional safety and complies with ISO/SAE 21434 cybersecurity requirements. The toolchain enables hybrid software development, permitting engineers to combine legacy C/C++ code with memory-safe Rust. Furthermore, the compiler includes planned Embedded AI capabilities to compile trained machine learning models directly into optimized code for the Parallel Processing Unit.

Virtual Prototyping and Ecosystem Integration
To accelerate software development prior to hardware availability, HighTec integrated its C/C++ platform into the DRIVECORE RISC-V virtual prototyping bundle. This software package includes the Synopsys Virtualizer Development Kit (VDK), Lauterbach TRACE32 debugging tools, peripheral drivers, and a FreeRTOS implementation. This allows early adopters to begin software migration and validation immediately.

HighTec’s multi-architecture approach allows developers to maintain a consistent toolchain across Infineon’s broader portfolio, including the AURIX, TRAVEO, and PSOC families. According to Mario Cupelli, CTO of HighTec EDV-Systeme GmbH, "Our safety- and security-qualified C/C++ and Rust toolchains, together with our planned Embedded AI support, enable customers to scale hardware and software, reuse existing code and develop robust and efficient safety-critical applications."

Additional Context
This section details technical specifications and competitive benchmarking not included in the original news release.

In the automotive compiler market for RISC-V architectures, HighTec competes primarily with Green Hills Software (MULTI IDE and optimizing compilers), IAR Systems (IAR Embedded Workbench for RISC-V), and Tasking. Competitive benchmarking in this sector evaluates ISO 26262 ASIL D certification, code density, and execution speed optimizations specific to the RISC-V instruction set architecture (ISA).

While open-source GCC and LLVM toolchains exist for RISC-V, commercial compilers like HighTec and IAR differentiate themselves through rigorous automotive safety qualifications and proprietary optimizations for specific silicon implementations. For example, both IAR and HighTec offer ASIL D certification and support for the RV32 and RV64 ISAs. However, HighTec’s explicit integration of Rust—a language increasingly mandated by automotive OEMs for its memory safety guarantees—provides a distinct advantage over legacy toolchains that rely solely on C/C++ static analysis (like MISRA C) to prevent memory leaks and buffer overflows. Furthermore, the integration of edge AI model compilation directly into the toolchain addresses the growing requirement to execute neural networks on dedicated MCU co-processors, competing with separate AI deployment frameworks like STMicroelectronics' STM32Cube.AI.

Edited by Aishwarya Mambet, Induportals Editor, with AI assistance.

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