Synopsys Empowers European Semiconductor Innovators with Advanced Chip Design Tools

Synopsys and the European Chips Joint Undertaking (Chips JU) formed an agreement to deliver electronic design automation (EDA) software to European startups and small-to-medium enterprises via the European Chips Design Platform (EuroCDP). This framework supports design workflows targeting high-performance computing, artificial intelligence, automotive engineering, and industrial automation.

Engineering Challenge and Partnership Rationale
Developing advanced system-on-chip (SoC) architectures requires access to high-tier silicon design, verification, and signoff suites. Early-stage hardware enterprises and research teams frequently face capital constraints and complex licensing barriers when attempting to access production-grade digital infrastructure.

To prevent development bottlenecks within the European semiconductor ecosystem, the partnership pairs EuroCDP infrastructure — including intellectual property blocks, training, funding, and prototyping coordination — with Synopsys computational design environments. This combined model gives smaller development teams the same standard verification capabilities utilized by global semiconductor manufacturers.

Technical Platform and Toolchain Capabilities
Under this framework, Synopsys supports Level 1 and Level 2 phases of the EuroCDP program, establishing continuity from early architecture exploration through to pre-production signoff. The tool suite covers:

Full digital front-end and back-end flows for leading-edge foundry process nodes.

Photonic integrated circuit (PIC) design flows addressing optical networking, data center interconnects, and sensing.

Analog and mixed-signal (AMS) verification flows for automotive, power control, and industrial connectivity systems.

Power-integrity analysis and optimization technologies to verify power delivery, operational efficiency, and thermal stability in silicon implementations.

Pre-production Integration and Ecosystem Impact
The initiative lowers capital expenditure barriers and accelerates time-to-tape-out across advanced node developments. By standardizing design flows against foundry process design kits (PDKs), participant ventures reduce the cycle time needed to transition prototypes to commercial fabrication.

Existing European developers, including Axelera AI, have utilized these implementation workflows alongside Ansys power-integrity software to develop specialized processing units, demonstrating functional optimization across power, performance, and silicon area.

Industry Stakeholder Integration
"EuroCDP is designed to give startups, SMEs and research teams a clearer pathway to the resources they need to develop new technologies," said Jari Kinaret, Executive Director of the Chips Joint Undertaking. "Expanding the platform with Synopsys' advanced design capabilities is an important part of making Europe's chip innovation ecosystem more accessible and dynamic."

Antonio Varas, Chief Strategy Officer at Synopsys, noted: "By joining the initiative, Synopsys is helping EuroCDP members accelerate their design process, contributing to the goals of the European Chips Act and a stronger, more competitive European semiconductor ecosystem."

Cooperation technical milestones and ecosystem roadmaps will be presented during the European Industrial Alliance on Semiconductors annual conference in Brussels, Belgium, featuring technical panels covering design acceleration methods in the region.

Edited by Evgeny Churilov, Induportals Media - Adapted by AI.

www.synopsys.com