Keysight Presents Secure Boot ETSI Standard at electronica

At this year's electronica (Booth A4-506), Keysight Technologies is highlighting its contributions to addressing the upcoming EU Cyber Resilience Act (CRA). To support manufacturers in implementing strict cybersecurity requirements, the company actively participated in developing the new ETSI standard EN 304 623 for Secure Boot Managers. Since the system boot is the first line of defense for a connected device, a secure boot manager ensures that only trusted code is executed. The draft standard, whose formal publication is expected in 2027, translates complex regulatory expectations into 99 verifiable security requirements and standardized cryptographic protective measures.

Field-Tested Security Tests and Fault Injection
Keysight's contribution to this standard is based on the deep experience of its Device Security Lab, which specifically tests secure boot implementations against advanced attack techniques like fault injection. According to Marc Witteman, Technical Director at Keysight, boot managers face constant threats at the hardware, firmware, and network levels, which is why industry-wide collaboration was essential. By combining this new regulatory framework with Keysight's practical testing expertise, manufacturers can build a seamless "Chain of Trust" and efficiently develop robust, CRA-compliant products to market readiness.

Additional Context: Hardware-Based Chains of Trust and Fault Injection
This section describes cryptographic principles and hardware attack vectors not included in the original press release.

In embedded security, the "Secure Boot" process forms the foundation of the so-called "Root of Trust" (RoT). The very first code executed when a microcontroller is powered on is loaded from an immutable ROM (Read-Only Memory). This code verifies the cryptographic digital signature of the subsequent bootloader using public keys hardwired in eFuses or Secure Elements. Only after successful verification is control passed to the next stage, creating an unbroken Chain of Trust up to the operating system.

Hackers often attempt to bypass this critical verification step through "Fault Injection". This technique uses precisely timed physical disturbances—such as extremely short voltage drops (voltage glitching), electromagnetic pulses (EMP), or laser pulses on the silicon—to disrupt the processor at the exact clock cycle when it evaluates the signature verification result. A successful glitch can cause the chip to incorrectly execute a conditional jump instruction and load manipulated malware, even though the cryptographic signature was actually invalid. Therefore, CRA-compliant boot managers must not only be securely programmed on the software side but also demonstrate provable resilience against such physical hardware manipulations at the silicon level.

Edited by industrial journalist Lekshman Ramdas, with AI assistance.

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