PCIe 7.0 Receiver Testing for 128 GT/s Systems

Keysight Technologies has introduced a new test application for PCIe 7.0 receivers, extending its portfolio for high-speed validation. The solution addresses increasing challenges in validating PCIe 7.0 receivers operating at 128 GT/s, particularly for next-generation computing, AI, and data center platforms.

As PCIe 7.0 adoption accelerates and development cycles continue to shorten, requirements for signal integrity and high-speed interface validation are becoming more demanding. Developers face increasing complexity in generating precise stress signals and validating receiver performance under realistic operating conditions.

PCIe 7.0 Receiver Validation at 128 GT/s
The new receiver test application extends Keysight’s existing PCIe 7.0 test environment with calibration and control functions for stress signals. The objective is to enable reliable validation of ASIC receivers operating in common-clock mode at data rates up to 128 GT/s.

The solution combines the M8050A BERT product family with the M8042A 120-GBaud pattern generator and the M8043A error analyzer. This hardware platform enables precise generation and analysis of high-frequency signals for PCIe 7.0 receiver characterization.

The hardware is complemented by the new N5991PB7A software application. The software automates calibration and control processes for PCIe 7.0 receiver stress signals, reducing manual setup effort during validation. According to Keysight, this improves measurement repeatability and increases reliability during ASIC characterization.

Automated High-Speed Testing for AI and Data Center Architectures
The increasing bandwidth requirements of AI accelerators, high-performance computing systems, and hyperscale data center infrastructures are placing greater demands on PCIe interconnect technologies. PCIe 7.0 doubles the data rate of PCIe 6.0 to 128 GT/s, increasing the importance of receiver validation for signal attenuation, jitter, and channel loss performance.

Keysight addresses these challenges through automated PCIe 7.0 RX workflows. Automated calibration reduces setup time and accelerates validation of complex ASIC designs.

According to the company, standards-compliant stress-signal generation helps identify potential receiver weaknesses early in the development cycle. This reduces rework during later development stages and minimizes compliance risks.

End-to-End PCIe 7.0 Validation Coverage
The new receiver test solution complements Keysight’s existing PCIe 7.0 transmitter test platform, extending end-to-end validation coverage across both transmitter and receiver layers within the PCIe 7.0 physical interface.

Dr. Joachim Peerlings, Vice President of Network and Data Center Solutions at Keysight, stated that validating PCIe 7.0 receivers at 128 GT/s represents one of the industry’s largest signal integrity challenges. He added that the expanded portfolio is intended to help developers reduce risks and accelerate validation of next-generation ASIC designs.

The solution is aimed primarily at developers of high-performance ASICs, AI accelerators, networking hardware, and server platforms preparing for future PCIe 7.0 infrastructures.

Additional Context: Technical Specifications and Competitive Benchmarking
PCIe 7.0 uses PAM4 signaling technology and supports data rates of 128 GT/s per lane, delivering bidirectional bandwidths of up to 512 GB/s in x16 configurations. The specification was developed to address growing bandwidth requirements in AI workloads, hyperscale data centers, and high-performance computing environments.

In the high-speed test and measurement market, Keysight competes with companies including Anritsu, Tektronix, and Rohde & Schwarz. Comparable PCIe validation platforms are typically evaluated based on maximum baud rate support, jitter injection capabilities, automation features, and compliance with PCI-SIG specifications.

Keysight differentiates its solution through the integration of hardware BERT systems with automated calibration software for PCIe 7.0 receiver stress testing. The combination of a 120-GBaud signal generator and automated stress-signal calibration targets increasingly demanding requirements associated with PAM4-based high-speed ASIC validation.

Edited by Sucithra Mani, Induportals editor – adapted by AI.

www.keysight.com