Broadcom Ships Industry First 2nm Custom Compute SoC for AI

The 2nm custom compute SoC is the first implementation of the 3.5D eXtreme Dimension System in Package (XDSiP) platform, designed to address the computational requirements of gigawatt-scale artificial intelligence (AI) infrastructures. This technology is primarily applicable to the development of next-generation accelerators (XPUs) used in hyperscale data centers and high-performance computing (HPC) environments. By integrating 2.5D packaging techniques with 3D-integrated circuit (3D-IC) architectures, the platform facilitates the scaling of compute, memory, and network input/output (I/O) within a condensed physical footprint.

Technical Architecture and Face-to-Face Integration
The 3.5D XDSiP platform utilizes Face-to-Face (F2F) bonding technology to achieve vertical integration between logic and memory dies. This mechanism reduces the distance electrical signals must travel compared to traditional lateral 2.5D layouts, resulting in higher signal density and reduced interconnect latency. The transition to a 2nm process node further improves power efficiency, allowing for higher transistor density while maintaining the thermal envelopes required for dense server racks.

In the context of the automotive data ecosystem and broader industrial AI, these hardware advancements allow for the processing of massive datasets with lower energy overhead. The modular nature of the XDSiP platform enables independent scaling of components, which means memory bandwidth can be increased without necessitating a proportional increase in the logic die size. This flexibility is critical for tailoring hardware to specific machine learning workloads that may be memory-bound or compute-bound.

Implementation in Fujitsu-Monaka and Industry Applications
Fujitsu has integrated this 3.5D technology into its FUJITSU-MONAKA initiative, which focuses on delivering low-power, high-performance processors for sustainable AI-driven infrastructure. The use of F2F 3D integration within this project provides a measurable increase in compute density, essential for managing the digital supply chain of data required by large language models and complex simulations.

According to technical specifications from Broadcom’s ASIC Products Division, the 3.5D platform capabilities have been expanded to support a wider customer base for XPUs scheduled for shipment in the second half of 2026. This timeline follows the initial introduction of the XDSiP platform technology in 2024, marking a two-year transition from conceptual platform to 2nm silicon production.

Performance Benchmarks and Scalability
While traditional 2.5D packaging relies on organic substrates or silicon interposers to connect side-by-side dies, the 3.5D approach incorporates active silicon stacking. This configuration supports superior power delivery and thermal management by distributing heat across multiple layers more effectively than single-layer high-density chips. The resulting chips are capable of supporting the high-frequency switching required for real-time AI inference and training at scale, providing a hardware foundation for the next generation of global computing infrastructure.

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